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1. Verification Methodology Manual for SystemVerilog
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Author:
Bergeron, Janick; Cerny, Eduard; Hunter, Alan; Bergeron, Janick; Cerny, Eduard; Hunter, Alan; Nightingale, Andy
Publisher:
Springer US 2006
Format:
e-book
2. SVA: The Power of Assertions in SystemVerilog
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Author:
Cerny, Eduard; Dudani, Surrendra; Havlicek, John; Havlicek, John; Korchemny, Dmitry; Korchemny, Dmitry
Publisher:
Springer International Publishing 2015
Format:
e-book