The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits

MLA

Jespers, Paul G. The G M /i D Methodology, A Sizing Tool for Low-voltage Analog Cmos Circuits. Springer US, 2010.

APA

Jespers, P. G. (2010). The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits. Springer US.

Chicago

Jespers, Paul G. The g m /I D Methodology, A Sizing Tool for Low-Voltage Analog CMOS Circuits. : Springer US, 2010.