Logic Synthesis and SOC Prototyping: RTL Design using VHDL

MLA

Taraate, Vaibbhav. Logic Synthesis and Soc Prototyping: Rtl Design Using Vhdl. Springer Singapore, 2020.

APA

Taraate, V. (2020). Logic Synthesis and SOC Prototyping: RTL Design using VHDL. Springer Singapore.

Chicago

Taraate, Vaibbhav Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. : Springer Singapore, 2020.