MARC Record
Leader
001
001926795
003
BE-GnUNI
005
20230728134203.0
008
060927s2004 ||||||||||||||||| ||eng||
020
a| 013039985X
040
a| Howest
041
0
a| eng
080
a| 681.32.062
245
0
0
a| Digital system design with VHDL.
250
a| 2nd ed.
260
a| Harlow :
b| Prentice Hall,
c| 2004.
300
a| XIII, 368 p.
520
a| Preface Introduction. Combinational Logic Design. Combinational Logic using VHDL Gate Models. Combinational Building Blocks. Synchronous Sequential Design. VHDL Models of Sequential Logic Blocks. Complex Sequential Systems. Simulating VHDL. VHDL Synthesis. Testing Digital Systems. Design for Testability. Asynchronous Sequential Design. Interfacing with the Analogue World. Appendix A VHDL Standards.Appendix B Verilog Appendix C Shared Variable packages Bibliography Answers to selected exercises
650
4
a| VHDL (vhsic hardware description language).
700
1
a| Zwolinski, Mark,
d| ....-
0| (viaf)
852
4
b| HWPNT
c| PENTA
j| PENTA.ELA.681.32.062
p| 3009587
920
a| book