MARC Record
Leader
001
001927168
003
BE-GnUNI
005
20230809091640.0
008
070112s2002 ||||||||||||||||| ||eng||
020
a| 0792376722
040
a| Howest
041
0
a| eng
080
a| 621.39
080
a| 681.32.062
084
a| 663.43
2| vsiso
245
0
0
a| Verilog quickstart :
b| a practical guide to simulation and synthesis in Verilog.
250
a| 3rd edition
260
a| New York :
b| Springer,
c| 2002.
300
a| XXII, 355 p.
e| cd-rom.
490
0
a| The Kluwer international series in engineering and computer science
520
a| List of Figures. List of Examples. List of Tables. 1. Introduction. 2. Introduction to the Verilog Language. 3. Structural Modeling. 4. Behavioral Modeling. 5. Operators. 6. Working with Behavioral Modeling. 7. User-Defined Primitives. 8. Parameterized Modules. 9. State Machines. 10. Modeling Tips. 11. Modeling Style Trade-Offs. 12. Test Benches and Test Management. 13. Common Errors. 14. Debugging a Design. Appendix A: Gate Level Details. Appendix B: Example Summary. Index.
650
4
a| Logische schakelingen.
700
1
a| Lee, James M.,
d| ....-
0| (viaf)
852
4
b| HWPNT
c| PENTA
j| PENTA.663.43 LEE 02
p| 3009836
920
a| book