MARC Record
Leader
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001927336
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BE-GnUNI
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20230808133508.0
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070301s2005 ||||||||||||||||| ||eng||
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a| 007144372X
040
a| Howest
041
0
a| eng
080
a| 621.39
084
a| 663.43
2| vsiso
245
0
0
a| Applied formal verification.
260
a| New York :
b| McGraw-Hill,
c| 2005.
300
a| XIV, 237 p. :
b| ill.
520
a| PREFACE Chapter 1: Introduction to Verification Chapter 2: Verification Process Chapter 3: Current Verification Techniques Chapter 4: Introduction to Formal Techniques Chapter 5: Formal Basics and Definitions Chapter 6: Property Specification Chapter 7: The Formal Test Plan Process Chapter 8: Techniques for Proving Properties Chapter 9: Final System Simulation APPENDIX A: IEEE 1850 PSL PROPERTY SPECIFICATION LANGUAGE APPENDIX B: IEEE 1800 SYSTEM VERILOG ASSERTIONS BIBLIOGRAPHY INDEX
650
4
a| Digitale elektronica.
650
4
a| Geïntegreerde schakelingen.
650
4
a| Logische schakelingen.
700
1
a| Perry, Douglas L.,
d| ....-
0| (viaf)
700
1
a| Foster, Harry D.,
d| 1956-
0| (viaf)117013910
852
4
b| HWPNT
c| PENTA
j| PENTA.663.43 PERR 05
p| 3009891
920
a| book