MARC Record
Leader
001
001928344
003
BE-GnUNI
005
20230808133508.0
008
080414s2002 ||||||| |||||||||||eng||
020
a| 0071400702
040
a| Howest
041
0
a| eng
080
a| 681.32.062
245
0
0
a| VHDL :
b| programming by example.
250
a| 4th ed.
260
a| New York :
b| McGraw-Hill,
c| 2002.
300
a| XVII, 476 p.
e| cd-rom
520
a| Chapter 1: Introduction to VHDL Chapter 2: Behavioral Modeling Chapter 3: Sequential Processing Chapter 4: Data Types Chapter 5: Subprograms and Packages Chapter 6: Predefined Attributes Chapter 7: Configurations Chapter 8: Advanced Topics Chapter 9: Synthesis Chapter 10: VHDL Systems Chapter 11: High Level Design Flow Chapter 12: Top-Level System Design Chapter 13: CPU: Synthesis Description Chapter 14: CPU: RTL Simulation Chapter 15: CPU Design: Synthesis Results Chapter 16: Place and Route Chapter 17: CPU: VITAL Simulation Chapter 18: At Speed Debugging Techniques Appendix A: Standard Logic Package Appendix B: VHDL Reference Tables Appendix C: Reading VHDL BNF Appendix D: VHDL93 Updates
650
4
a| VHDL (vhsic hardware description language).
700
1
a| Perry, Douglas L.,
d| ....-
0| (viaf)
852
4
b| HWPNT
c| PENTA
j| PENTA.ELA.681.32.06 PERR 02
p| 3010561
920
a| book