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MARC Record

Leader
001 001928345
003 BE-GnUNI
005 20230728134203.0
008 080414s2007 ||||||||||||||||| ||eng||
020
  
  
a| 9780071475464
040
  
  
a| Howest
041
0
  
a| eng
080
  
  
a| 681.39.4
084
  
  
a| 663.12 2| vsiso
245
0
0
a| VHDL : b| modular design and synthesis of cores and systems.
250
  
  
a| 3rd ed.
260
  
  
a| New York : b| McGraw-Hill, c| 2007.
300
  
  
a| XVIII, 531 p.
520
  
  
a| Chapter 1: Digital System Design Automation with VHDL Chapter 2: RTL with VHDL Chapter 3: VHDL Constructs for Structure and Hierarchy Descriptions Chapter 4: Concurrent Constructs for RT Level Descriptions Chapter 5: Sequential Constructs for RT Level Descriptions Chapter 6: VHDL Language Utilities and Packages Chapter 7: VHDL Signal Model Chapter 8: Hardware Cores and Models Chapter 9: Core Design and Testability Chapter 10: Design, Test and Application of a Processor Core APPENDIX A: VHDL KEYWORDS APPENDIX B: VHDL LANGUAGE GRAMMAR APPENDIX C: VHDL STANDARD PACKAGES APPENDIX D: STD_LOGIC_1164 Package APPENDIX E: STD_LOGIC_TEXTIO Package APPENDIX F: STD_LOGIC_ARITH Package APPENDIX G: STD_LOGIC_SIGNED APPENDIX H: STD_LOGIC_UNSIGNED APPENDIX I: math_real Package
650
  
4
a| VHDL (vhsic hardware description language).
700
1
  
a| Navabi, Zainalabedin, d| ....- 0| (viaf)65665639
852
4
  
b| HWPNT c| PENTA j| PENTA.663.12 ZAIN 07 p| 3010554
920
  
  
a| book
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