MARC Record
Leader
001
001928661
003
BE-GnUNI
005
20230803092350.0
008
080819s2005 ||||||||||||||||| ||eng||
020
a| 9781852338992
040
a| Howest
041
0
a| eng
080
a| 681.32
084
a| 521.4
2| vsiso
245
0
0
a| System-level test and validation of hardware/software systems.
260
a| London :
b| Springer,
c| 2005.
300
a| XII, 179 p. :
b| ill.
490
0
a| Springer series in advanced microelectronics
520
a| "System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors); and design for testability." For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.
700
1
a| Sonza Reorda, M.,
d| ....-
0| (viaf)
700
1
a| Peng, Z.,
d| ....-
0| (viaf)
700
1
a| Violante, M.,
d| ....-
0| (viaf)
852
4
b| HWPNT
c| PENTA
j| PENTA.521.4 SONZ 05
p| 3010915
920
a| book