MARC Record
Leader
001
001928662
003
BE-GnUNI
005
20230809091643.0
008
080819s2005 ||||||||||||||||| ||eng||
020
a| 9781402032073
040
a| Howest
041
0
a| eng
080
a| 621.38
084
a| 663.12
2| vsiso
245
0
0
a| Introduction to advanced system-on-chip test design and optimization.
260
a| Dordrecht :
b| Springer,
c| 2005.
300
a| XV, 388 p. :
b| ill.
490
0
a| Frontiers in electronic testing
520
a| SOC test design and its optimization is the topic of "Introduction to Advanced System-on-Chip Test Design and Optimization". It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: test concepts, SOC design for test, and SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.
700
1
a| Larsson, Erik,
d| ....-
0| (viaf)
852
4
b| HWPNT
c| PENTA
j| PENTA.663.12 LARS 05
p| 3010925
920
a| book