Logic Synthesis and SOC Prototyping: RTL Design using VHDL
Full text!- Type:
- e-book
- Titel:
- Logic Synthesis and SOC Prototyping: RTL Design using VHDL
- Taal:
- Engels
- Uitgever:
- Springer Singapore 2020
- ISBN:
- 981-15-1313-9
981-15-1314-7 - Permalink:
- http://bibtest.howest.be/catalog/ebk03:4940000000158732
